1. Field of the Invention
The present invention relates to a powering circuit for a MOS (metal oxide semiconductor) technology integrated circuit, especially a C-MOS (complementary MOS) technology integrated circuit.
2. Description of the Prior Art
In certain types of integrated circuits, especially those containing flip-flops, it is important for some points of the circuit to have a well-defined logic states when the circuit is powered after an interruption in the power supply. For it is necessary to prevent uncertain or wrong logic states from appearing during the application of the supply voltage and from subsequently being reflected in the operation of the circuit.
The states of the nodes of the logic circuit cannot really have a definite value unless the supply voltage of the circuit exceeds a minimum value. For example, for a C-MOS technology logic circuit, this minimum value is 3 volts. For a smaller voltage, the nodes have variable potentials which depend more on the capacitive couplings of the circuit than on purely logical data. Furthermore, these potentials will differ from one circuit to another for batch-produced circuits.
Therefore, a powering circuit is used to remove this drawback. This circuit delivers a positioning pulse when the supply voltage has reached a value sufficient to enable the positioning of the logic circuit through a no-load operating cycle. Powering circuits currently available are generally complicated because there is no stabilized supply voltage. They are most commonly made by using the threshold voltages of MOS transistors, capacitor charges and numerous loops with positive and negative feedbacks.
An object of the present invention is to propose a new powering circuit which is particularly simple and efficient as compared with prior art powering circuits.